Job description: • Create high performance, high frequency digital and mixed signal designs and drive from synthesis to tapeout. • Responsible for feasibility analysis, wiring studies, floor-planning, chip assembly, synthesis, place & route, integrating custom/analog blocks, timing, power analysis, design signoff and GDS release. • Work with the Boston Physical Design team to contribute to the development of a robust place and route flow/methodology that handles the challenges of power grid infrastructure, design floorplanning, Clock and Signal Routing, STA analysis and closure, and backend design verification. • Work with team members across all disciplines to optimize all physical aspects of the design. Preferred Qualifications: • BS or MS in a relevant discipline such as Electrical Engineering and at least 2-5 years experience • Experience in P&R and Physical Design deep sub-micron technologies, at 1GHz or higher clock frequencies • Track record of successful tapeouts of ASICs of significant scope (technology node, die size, frequency, power) • Experience with SoC challenges such as multiple clock, multiple power domains is a plus. • Excited to work in an energetic environment with a talented and enthusiastic team! • English fluency: high
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