Job Responsibilities: 1.Validate, debug, and understand PCIe/ CXL link training (LTSSM), Data Link Layer (DLLP), and Transaction Layer (TLP). 2.Plan, develop, and execute PCIe/ CXL compliance test plans 3.System level debugging of hardware and software issues 4.Build and support validation infrastructure through the development of embedded software, device drivers, and test tools Required: 1.Bachelor or Master degree in CS, CE, EE with 5+ yrs. 2.Good Knowledge of PCI Express/CXL system architecture. 3.Good Knowledge of ACPI. 4.Excellent knowledge of PCIe / CXL code in BIOS and Kernel. 5.Proficient in C / Python programming. Preferred: 1.Excellent knowledge of digital systems and computer architecture 2.Experience in use of lab equipment (e. g., protocol analyzers/exercisers) 3.Excellent verbal and written communication skills
云计算芯片公司,主要产品DDR
职位顾问