Support products from design through production by evaluating and tailoring CMOS foundry processes to product needs. Introduce new process tech and integrate with company product roadmap goals. Assess foundry (digital, analog) device performance capabilities. Primary interface between foundries and internal team for tapeouts and all other needs. Procure all necessary foundry collateral such as LVS runsets, PDKs, DRC rule decks. Work with foundries to solve potential insufficiencies in design rules and runsets. Work with design team to make product performance and yield improvements through the foundry layout and tape-out processes. Requirements Deep understanding of silicon device physics, device characterization and wafer fab processes. Understanding of LVS/DRC and tapeout flows. Experience with software to read and edit mask layout data (e.g. Cadence Virtuoso software). Experience with statistical data processing software (e.g. R or JMP). Experience with photo lithography process and tool is a plus. Ability to work in a fast-paced environment with minimal supervision. Good team player that willing to work with peers. Good project management skills to work with design teams on multiple projects simultaneously.
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