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职位描述

Job description:

• Develop verification collateral suitable for a variety of design implementations ranging from FPGAs to SOCs

• Drive DV tasks such as test planning and execution, coverage for digital and mixed-signal blocks

• Construct and execute test plans and perform coverage analysis

• Work closely and collaboratively with RTL and analog designers

• Work with US DV team to maintain and contribute to DV methodology and best practices

Preferred Qualifications:

• BS or greater in a relevant discipline such as Computer Science, Electrical Engineering, or Computer Engineering with at least 3 years of relevant work experience

• Logic simulation skills including testbench design, stimulus generation, coverage closure, equivalence-checking and debug

• Proficiency in UVM/VMM/eRM and a hardware description language such as SystemVerilog

• Strong software skills (C, C++, Python) to develop and support infrastructure and flows

• Experience with formal verification a plus

• Experience with mixed-signal simulation and/or modeling a plus

• Basic knowledge of Deep Neural Networks and Artificial Intelligence a plus

• English Fluency: Plus

企业介绍

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工作地址

职位对接人

猎头公司职位顾问-科瀚纳猎头公司

Molly

职位顾问

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